A memory device may be categorized as a static random access memory (SRAM) or a dynamic random access memory (DRAM). The memory device is usually constructed as an array of memory cells. Information data bits are stored in each memory cell with corresponding voltage levels retained therein. A basic SRAM memory cell generally includes a pair of cross-coupled inverters serving as a latch to store data bits. In a six-transistor (6T) memory cell, the inverters may be accessible through a single-port read/write operation in which one read operation or one write operation is allowed for accessing one memory cell. Moreover, multiple sets of access transistors may be incorporated for implementing multi-port read operations in which multiple data readings are performed on a single or multiple memory cells at the same time.